1. Field of the Invention
The present invention relates to a TAB tape semiconductor device formed by mounting a semiconductor integrated circuit chip in a device hole formed in a TAB tape and, more particularly, to a TAB tape semiconductor device which is formed to obtain a good test result.
2. Description of the Prior Art
A semiconductor integrated circuit, e.g., an exclusive IC such as an ASIC (Application Specific Integrated Circuit), is provided to the user usually in the form of a QFP (Quad Flat Package). In a conventional QFP, packaging is performed by connecting a semiconductor integrated circuit chip and a lead frame in accordance with wire bonding. In a peripheral type package such as a QFP, as the number of pins increases, the pitch of the pins becomes narrow, and it has become difficult to perform packaging with a method using wire bonding. For this reason, connection between the chip and the lead frame is made by using a semiconductor device called a TCP in which a semiconductor chip is mounted on a TAB tape. In this case, TCPs are usually separated into unit TCPs. Each unit TCP is mounted on a frame called a carrier, and is sent to an assembly process.
FIG. 1 is a plan view showing a conventional TAB tape semiconductor device. A TAB tape is formed of a resin tape 2 made of polyimide or the like, and wiring patterns 4 formed on it. A device hole 3 for mounting an integrated circuit chip therein is formed at the central portion of the resin tape 2. One end of each wiring pattern 4 has an inner lead 6 extending to the device hole 3 in a cantilever manner. A test pad 5 is formed on the other end of each wiring pattern 4. An integrated circuit chip 1 is mounted in the device hole 3, and chip pads 9 on the integrated circuit chip 1 are bonded to the distal end portions of the inner leads 6. The TAB tape on which the integrated circuit chip is mounted (this is called a TCP) is set on a carrier 7. Although a few wiring patterns are shown in FIG. 1 for the sake of illustrative convenience, about 500 to 800 leads are typically provided.
In the state shown in FIG. 1, a test is performed by using a testing system, e.g., an LSI tester. Since the number of pins increases, the packaging cost of the semiconductor device increases. The test is accordingly expected to perform highly precise evaluation. Due to the increase in the number of pins, the number of contacts in a relay portion extending from the LSI tester to the semiconductor device inevitably increases, and the wiring length increases accordingly. Therefore, a blunt or distortion in waveform has become serious. FIG. 2 is an equivalent circuit diagram showing the connection relationship between an LSI tester 20 and the integrated circuit chip 1 in the test.
As shown in FIG. 2, an input signal and a power supply voltage are supplied from an LSI tester 20 side driver 101 to an integrated circuit chip 1 side input circuit 105 through a test board transmission circuit 102a, a socket portion delay circuit 103a, and a TAB tape portion delay circuit 104a. A signal output from an integrated circuit chip 1 side output circuit 106 is input to an LSI tester 20 side comparator 107 through a TAB tape portion delay circuit 104b, a socket portion delay circuit 103b, and a test board transmission circuit 102b.
As the area of the semiconductor integrated device increases and the number of pins thereof increases, the size of the TAB tape increases, and the patterns on the TAB tape become narrow and elongated. As a result, the inductance component and capacitance component in the equivalent circuit of FIG. 2 increase to degrade the measurement environment. On the other hand, the operation speed of the semiconductor integrated circuit device increases, and accordingly a test for the semiconductor integrated circuit device at a high frequency has reached limitations.
As described above, as the size of the package increases and the number of pins increases, the assembly cost increases, and accordingly a TCP need be sufficiently tested. To sufficiently test a large-scale semiconductor integrated circuit device, a very large number of test patterns must be supplied at a high speed with waveforms free from a blunt or distortion.
The problem that should be solved by the present invention is to perform a high-precision test at a high frequency in a measurement environment which is degraded in accordance with an increase in size and operation speed of a semiconductor integrated circuit device and with an increase in size of a TAB tape, such that the test and evaluation are not adversely affected by degradation in signal waveform in a transmission circuit extending from the tester to the semiconductor integrated circuit device as a test target.